| 摘要 |
A multi-chip module (10), having n semiconductor chips 141 - 14n, each chip having a Boundary-Scan architecture, is rendered Boundary-Scan-compliant both as a circuit board and as a macro-device by the addition of a bypass circuit (36, 36' and 36''). During selected intervals when the module (10) is to be Boundary-Scan-compliant as a macro-device, the bypass circuit operates to bypass the Test Data Input (18) to the Test Data Output (34) of each of n-1 chips. During other than the selected intervals, the bypass circuit allows test information applied to the Test Data Input of each of the chips to be shifted through the chip and to appear at its Test Data Output to facilitate Boundary-Scan compliance of the module as a circuit board. |
