Phasenkomparator

摘要

Apparatus for transfer of data between devices having different clock frequencies includes a first processor coupled to a first system bus to provide data to a cache and a memory, and a second processor coupled to the first system bus and a second abbreviated system bus to receive read data from said first system bus, and a means for correcting errors in memory. Also included are a counter, means for detecting a selected state of said counter, and means, responsive to output signals from said counter, for selectively permitting or inhibiting transfer of data fed to a recirculating state device. The apparatus includes a first means for providing a first clocking signal, a second means for providing a second clocking signal, means for providing an error signal responsive to an offset between edges of the first and second clocking signals.