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发明名称
PLL FREQUENCY SYNTHESIZER CIRCUIT COMPARISON FREQUENCY DIVIDER AND SWALLOW COUNTER
摘要
申请公布号
KR100210251(B1)
申请公布日期
1999.07.15
申请号
KR19970002481
申请日期
1997.01.28
申请人
FUJITSU LIMITED
发明人
AISAKA, TETSUYA
分类号
H03L7/197;H03K21/40;H03K23/66;H03L7/08;H03L7/183;H03L7/193;(IPC1-7):H03L7/08
主分类号
H03L7/197
代理机构
代理人
主权项
地址
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