| 摘要 |
<p>An annihlation based logic gate (500) which evaluates the complementary sense of a high fanin ANDing function (i.e., an OR function). First (506) and second (508) nodes are precharged (502, 504) during a precharge phase of the clock. During an evaluate phase of the clock, discharge (510) of the first node is begun substantially simultaneously with evaluation of the complementary OR function. If the complementary OR function evaluates true, the second node is pulled down so as to cancel discharge of the first node. The circuit may be timed so that evaluation of the complementary OR function occurs just prior to the first node's being discharged beyond a trigger point of an output inverter (518). The output (520) thus transitions in a monotonic fashion. <IMAGE></p> |
