Coupled phase locked loops

摘要

A method and apparatus are provided for generating synchronized clock signals. According to the method and apparatus, first and second pluralities of signals are generated, having time-varying phase differences with respect to a reference clock. The first clock is supplied by a succession of signals from among the first plurality of signals, in which one of the signals succeeds another responsive to a first phase difference. The second clock is supplied by a second succession of signals from among the second plurality of signals. One signal in the second succession of signals succeeds another responsive to a second phase difference. The succession among the first plurality of signals is also responsive to the second phase difference. <IMAGE>