| 摘要 |
A multiple use core logic chip set is provided in a computer system that may be configured either as a bridge between an accelerated graphics port ("AGP") bus and host and memory buses, as a bridge between a remote peripheral component interconnect ("remote-PCI") bus and the host and memory buses, or as a bridge between a primary PCI bus and the remote-PCI bus. The function of the multiple use chip set is determined at the time of manufacture of the computer system or in the field whether an AGP bus bridge or a remote-PCI bus bridge is to be implemented. Selection of the type of bus bridge (AGP or remote-PCI) in the multiple use core logic chip set may be made by a hardware signal input, or by software during computer system configuration or power on self test ("POST"). Software configuration may also be determined upon detection of either an AGP or a remote-PCI device connected to the common AGP/remote-PCI bus.
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