发明名称 |
Fast clock generator and clock synchronizer for logic derived clock signals with synchronous clock suspension capability for a programmable device |
摘要 |
A programmable device includes a circuit for generating an asynchronous logic derived clock signal derived from one or more of a number of input signals. Circuits for synchronizing the asynchronous logic derived clock signal to a reference clock signal are coupled to the circuit for generating the asynchronous logic derived clock signal. The circuits for synchronizing generate a synchronized logic derived clock signal from the asynchronous clock signal and a reference clock signal. The programmable device further includes a circuit for suspending a clock signal. In one embodiment, a logic derived clock signal is generated and synchronized with a synchronous clock signal. In synchronizing the logic derived clock signal an intermediate signal is generated during a first clock cycle of the synchronous clock signal and is combined with the synchronized logic derived clock signal during a second clock cycle of the synchronous clock signal to produce a suspendable clock signal. The suspendable clock signal may be gated off in response to an input signal having a minimum duration of at least two clock cycles of the synchronous clock signal.
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申请公布号 |
US5923195(A) |
申请公布日期 |
1999.07.13 |
申请号 |
US19970828434 |
申请日期 |
1997.03.28 |
申请人 |
CYPRESS SEMICONDUCTOR CORP. |
发明人 |
GRAF, III, W. ALFRED |
分类号 |
H03K19/173;(IPC1-7):H03K17/22;H03L7/00 |
主分类号 |
H03K19/173 |
代理机构 |
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