| 摘要 |
PROBLEM TO BE SOLVED: To suppress the increase of power consumption with respect to reduction in a chip period length due to increase in a bit number of an information signal and increase in a spread multiple in a synchronization circuit that detects a peak value of an output from a matched filter to conduct synchronization acquisition and synchronization tracking. SOLUTION: After an absolute value circuit 3 obtains an absolute value of a correlation signal from a matched filter 2, a peak hold circuit 4 and a peak comparator 5 being analog circuits detect a peak level and provide a binary output of the result of detection, a reset counter 6 and a peak position counter 1 count a time between peak positions and a synchronization discrimination circuit 8 discriminates synchronization confirmation based on whether or not a period is a prescribed signal period. |
