| 摘要 |
For reducing the area for read/write bus lines to a half and shortening the length of the read/write bus lines so as to speed up the operation, the locating positions of input/output circuits for the corresponding bits, of memory blocks MB1 and MB3a located to oppose to each other and to interpose therebetween an active circuit area ACA and of memory blocks MB2a and MB4 located to oppose to each other and to interpose therebetween the active circuit area ACA, are made different from each other. Read/write bus lines RWB1 to RWB4 of the same length are formed and located to interconnect between the inputs/outputs for the corresponding bits, of the opposing memory blocks, by traversing an empty region between circuit blocks CB in the active circuit area ACA, and in such a manner that each two read/write bus lines extend between the memory blocks MB1 and MB2a and between the memory blocks MB3a and MB4.
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