| 摘要 |
A memory system for performing error detection and correction including a memory device that stores a plurality of data words, where each data word has a plurality of data bits and at least one associated check bit. The memory system further includes memory control circuitry that reads a plurality of data words in multiple cycles to form a block word that includes a sufficient number of check bits to perform detection of double bit errors and correction of single bit errors. A 72-bit block word is formed by grouping smaller data words retrieved from the memory device. For a 9-bit device with eight data bits and one check bit, eight burst cycles may be used to retrieve a 72-bit data block. Similarly, for 18-bit devices, four burst cycles may be used to retrieve the data block and for 36-bit devices, two burst cycles may be used to retrieve the data block. The memory system further includes error logic that receives and performs error detection and correction upon the block word. The error logic groups the check bits of the block word together, generates a syndrome code using a parity matrix, and uses the syndrome code and a corresponding syndrome table to detect and correct any bit errors in the data. |
