Method for eletronically representing a number, adder circuit and computer system

摘要

The invention relates to a method for electronically representing a number V in a binary data word. Both the exponent and the mantissa are represented as 2' complement. The mantissa is normalized to 0.1.F if the number V is positive where F is the fraction of the mantissa. In case that the number V is negative the fraction F is normalized to 10.F. Usage of this format allows to design an improved adder which requires less hardware.