| 摘要 |
A semiconductor integrated circuit device is provided, which is capable of further reduction in chip size without raising any bad effect to the function of the device, and deletion of the TEG region. A test element is formed on a semiconductor substrate. An insulating layer is formed on or over the substrate to cover the test element. An internal circuitry is formed on the substrate. A bonding pad is formed on the insulating layer. The test element is entirely or partially overlapped with the overlying bonding pad. The bonding pad includes a first part and a second part electrically insulated from each other. The first part of the bonding pad is electrically connected to the internal circuitry. The second part of the bonding pad is electrically connected to a terminal of the test element. On a verification test, one of the probes of a tester is contacted with the second part of the bonding pad, and another one thereof is contacted with the first part or an additional part thereof.
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