| 摘要 |
PROBLEM TO BE SOLVED: To reduce power consumption and speed-up the operation by composing an output buffer, with which the output level of a path transistor logic circuit is compensated, of a boot strap circuit. SOLUTION: When an input A.B (at a node (a)) from a path transistor logic circuit 1 is at an 'H' level, since an NMOS transistor T2 is conducted, an output vacuums an 'L' level. When the input A.B (at the node (a)) falls to the 'L' level, since an inverter output OUT (bar A.B) is charged by an NMOS transistor T3 , a potential is increased. Accompanying this increase, a potential at a node (b) is increased higher than a power supply voltage (VDD) by the effect of coupling with a boot strap capacitor CB and th NMOS transistor T3 is over driven. In this case, when the capacitance value of the capacitor CB is set at a suitable value, an inverter circuit not to generate the degradation of the output at the 'H' level can be constituted in the circuit configuration of composing the path transistor logic circuit of the NMOS transistors only. |
