发明名称 PLL SYNTHESIZER AND ITS CONTROL METHOD
摘要 PROBLEM TO BE SOLVED: To quicken transition/restoration to/from monitoring state of a radio wave with high precision not depending on an A/D converter and a D/A converter and to suitably suppress spurious radiation after restoration to the operating frequency. SOLUTION: A loop filter 3 being a component of a PLL is provided with a high speed time constant circuit 32 and low speed time constant circuits 33, 34. The time constant decided by the high speed time constant circuit 32 is a time constant suitable for high speed locking of an output frequency, and the time constant decided by the low speed time constant circuits 33, 34 is the one such that the output frequency is made stable by it and spurious radiation is suppressed. In the case of switching an output frequency f0 to a frequency to be monitored as soon, as the frequency is switched to the monitored frequency through the setting of a frequency division ratio with a switch Sa or Sb closed, the switch Sa or Sb is open. After the radio wave, monitoring while the switch Sa or Sb is open, the setting of the frequency division ratio is switched to that for the output frequency. After the lapse of a prescribed time, the switch Sa or Sb is closed.
申请公布号 JPH11191735(A) 申请公布日期 1999.07.13
申请号 JP19980294341 申请日期 1998.10.16
申请人 JAPAN RADIO CO LTD 发明人 YAMASHITA KAZUO;INOUE SHOJI;EGAWA MASAHIKO;SAKUMA HIROAKI;ADACHI MASAYUKI
分类号 H03B1/04;H03L7/107;H03L7/16;H03L7/18;H03L7/183;H03L7/187 主分类号 H03B1/04
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