发明名称 Jitter reducing circuit
摘要 A sync signal correction circuit generates a corrected sync signal which is obtained by correcting a timing of a sync signal on the basis of a time axis variation component (jitter component) of the sync signal separated from a picture signal. The corrected sync signal is used as the sync signal to cause a variation of time axis error of the picture signal to follow a variation of time axis error of an output signal of an automatic frequency control (AFC) circuit which constitutes a monitor device for reproducing and displaying the picture signal, such that the variation of time axis error of the output signal of the AFC circuit and the variation of time axis error of the picture signal of the reproduced picture signal are cancelled each other to prevent jittere from appearing on a display screen.
申请公布号 US5923377(A) 申请公布日期 1999.07.13
申请号 US19960755695 申请日期 1996.11.25
申请人 VICTOR COMPANY OF JAPAN, LTD. 发明人 KENMOCHI, TAKASHI;TAKESHITA, HIROSHI;UBUKATA, TSUNEO
分类号 H04N5/95;H04N5/932;H04N9/896;(IPC1-7):H04N7/00;H03L7/00;H04N5/04 主分类号 H04N5/95
代理机构 代理人
主权项
地址