| 摘要 |
A scale of circuit is reduced when a plurality of variable delay circuits are provided with respect to the same signal. A variable delay circuit is constructed such that variable delay circuit elements each comprising a delay circuit element composed of buffer gates each having an identical amount of delay connected in series and a selector e for selecting the input and output of the delay circuit element are connected in series in n-1 stages, wherein the number of the delay elements of the delay circuit element in each variable delay circuit element is 2i-1 (i: number of stages) in the order from the final stage. Other variable delay circuits are constructed such that the delay circuit element in the first stage of variable delay circuit elements in the one first stage of variable delay circuit elements of the one variable delay circuit is shared by the other variable delay circuits, and selectors for selecting the input and output of the delay circuit element and stages of variable delay circuit elements each comprising the delay circuit element composed of the delay elements connected in series and the selector for selecting the input and output of the delay circuit element are connected in series, wherein the number of the delay elements of the delay circuit element in each variable delay circuit element is 2i-1 (i: number of stages) in the order from the final stage.
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