| 摘要 |
A series-parallel A/D converter having a plurality of reference resistors, a first comparator section, a second comparator section, groups of switches, and lower-reference voltage lines. The reference resistors divide a full-scale voltage, generating different reference voltages. They are connected in series, forming blocks of resistors. The first comparator section compares an input voltage with upper reference voltages and selects one of the blocks of resistors in accordance with the result of comparison. The groups of switches applies the voltages at the nodes of the reference resistors of the selected block, to the lower-reference voltage lines. When the block BL0 is selected, voltages Vr0 and Vr8 are applied to the lower-reference voltage lines L0 and L8, respectively. When the block BL1 is selected, voltages Vr16 and Vr8 are applied to the lines L0 and L8, respectively. That is, the voltage applied through the line L8 remains unchanged, whichever block of resistors is selected.
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