Bi-layer silylation process

摘要

A new method of improving critical dimension control by using a silylation process with a cross-linked photoresist underlayer is described. A layer to be etched is provided on a semiconductor substrate wherein the surface of the layer has an uneven topography. The layer to be etched is coated with a first photoresist layer. The first photoresist layer is baked. The first photoresist layer is coated with a second photoresist layer. A portion of the second photoresist layer not covered by a mask is exposed to actinic light. Thereafter, the exposed portion of the second photoresist layer is baked, then silylated. The silylated portion of the second photoresist layer and the underlying first photoresist layer forms the photomask. The remaining second and first photoresist layers not covered by the photomask are etched away. The layer to be etched is etched away where it is not covered by the photomask and the photomask is removed to complete the photoetching having uniform critical dimension in the fabrication of an integrated circuit.