发明名称 MEMORY TESTING DEVICE
摘要 PROBLEM TO BE SOLVED: To generate only a first address by a pattern generator and to eliminates the need to generate following past addresses when a memory to be tested operates in a burst mode. SOLUTION: A burst address generating circuit 8 is added and then when the memory 3 to be tested operates in burst mode, all burst addresses are calculated by using the first address inputted from the pattern generator 2 and supplied to a fail memory 5 The burst address generating circuit 8 is provided with a circuit 9 which holds the first address, a counter 10, a computing element (adder) 11 which calculates all burst addresses from the output of the counter 10 and data of the address holding circuit 9, and a multiplexer 12 which switches and selects one of the output of the computing element 11 and the address signal of the pattern generator 2 and supplies it to the fail memory 5.
申请公布号 JPH11191080(A) 申请公布日期 1999.07.13
申请号 JP19970359625 申请日期 1997.12.26
申请人 ADVANTEST CORP 发明人 KUROSAKI HIROSHI
分类号 G06F12/16;G06F11/22;G11C29/56 主分类号 G06F12/16
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