Hamming value comparison for unweighted bit arrays

摘要

The comparators described herein comprise bit manipulation cells of a number of logic cells each built up of AND, OR etc. logic gates interconnected in parallel to make up one or more layers and do not rely on clocks, instead operating asynchronously. This makes the comparators highly robust and fault tolerant, and well suited for use as binary neurons in high integrity systems. They are less susceptible to radio frequency interference induced data corruption than alternative register-based implementations. Planar Hamming comparators capable of comparing two dimensional input arrays are also described.