发明名称 PHASE TRANSFER CIRCUIT
摘要 <p>PROBLEM TO BE SOLVED: To eliminate the need for a memory of a large capacity, such as a FIFO memory by receiving a digitized delay D so as to delay received data and to obtain in-device data. SOLUTION: A synchronization circuit 5 gives the position of a reference signal in each frame of input data 1 to a data hold section as input data position P. A delay in an in-device timing signal 7 with respect to the input data 1 is obtained, based on the input data position P and the in-device timing signal 7. The delay D is fed to a variable delay circuit 3. The variable delay circuit 3 delays the input data 1 by this delay D and provides an output of the delayed data.</p>
申请公布号 JPH11186996(A) 申请公布日期 1999.07.09
申请号 JP19970364443 申请日期 1997.12.18
申请人 OKI TEC:KK;OKI ELECTRIC IND CO LTD 发明人 KAWAMURA KAZUHIRO;TAKAHASHI TORU
分类号 H04L7/00;(IPC1-7):H04L7/00 主分类号 H04L7/00
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