| 摘要 |
<p>PROBLEM TO BE SOLVED: To reduce the power consumption of an information processor without incurring the deterioration of the effective performance of a program by controlling a clock frequency that is produced by a clock generator according to the load state of a bus. SOLUTION: When a CPU 2 accesses a peripheral processor 31 or 32, a bus protocol is generated through a bus 5. A bus access supervisory circuit 44 performs switching control of a clock frequency based on a result after supervising these bus protocols generated on the bus 5 through a supervisory signal line 48 for a specified time. That is, the circuit 44 reports the load state of the processor 31 or 32 which is supervised by the line 48 to a clock selective controller 41 through a control line 49. The circuit 41 instructs a clock generator 1 through a signal line 45 so that the generator 1 may choose an appropriate frequency. The generator 1 supplies a clock of a designated frequency to the CPU 2 and the processor 31 or 32.</p> |
