| 摘要 |
<p>PROBLEM TO BE SOLVED: To reduce a circuit scale by providing a counter which synchronies with a master clock to operate and a counter resetting circuit that is controlled by the outputs of a reset decoder and of a counter, and using the most significant bit in the counter as a clock output. SOLUTION: This circuit consists of an m-bit counter 3 which operates in synchronism with a master clock and of a counter resetting circuit 4 which is controlled by an output of a reset decoder 5 that is controlled by a clock selective signal and an output of the counter 3 and which outputs a reset signal for the counter 3. The circuit resets the counter 3 with a reset signal of the circuit 4 which is controlled by an output of the decoder 5 and an output of the counter 3, and makes the most significant bit in the counter 3 a clock output. The frequency of an outputted clock can be changed by a decoded value of the decoder 5.</p> |
