发明名称 CLOCK SIGNAL CONTROL CIRCUIT
摘要 <p>PROBLEM TO BE SOLVED: To prevent malfunction of a system due to an unstable clock signal caused at rising of a power supply in an electronic device such as a portable terminal. SOLUTION: The control circuit is provided with a pulse rate detection circuit 102 that detects it that an oscillator is stably oscillated, a clock supply selection circuit 103 that decides whether or not a clock signal is supplied to a clock operation circuit 104 based on an output of the detection circuit 102. Thus, the circuit 103 supplies the clock signal to the clock operation circuit 104 only when the pulse rate detection circuit 102 permits the supply of the clock signal.</p>
申请公布号 JPH11186885(A) 申请公布日期 1999.07.09
申请号 JP19970364078 申请日期 1997.12.17
申请人 NEC CORP 发明人 WATANABE MITSUHIRO
分类号 G06F1/08;G06F1/04;H03B5/32;H03K3/02;H03K5/00;H03K5/04;H03K5/19;H03L7/00;(IPC1-7):H03K5/04 主分类号 G06F1/08
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