| 摘要 |
PROBLEM TO BE SOLVED: To provide a Viterbi decoder which is small in circuit scale and is capable of high speed operation. SOLUTION: A path memory circuit 705 is provided with three RAMs (RAM10, RAM11, RAM12) with a dual port of, e.g. bit number = 8 and work number = 4, and path selection information s102 is written in the order of, e.g. RAM12→RAM11→RAM10→RAM12→RAM11,... for each clock under the control of a control circuit 101. On the other hand, the path selection information is read for each clock from the RAMs under the control of the control circuit 101 and given to a trace circuit 102 as read path selection information s105 or the like. The trace circuit 102 conducts tracing by 3 specified periods, based on the read path selection information, trace start state information s108 generated by the control circuit 101. Based on the trace result, decoded data and a trace start state for a succeeding blocks are obtained.
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