| 摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor storage device which facilitates control of switching of external clocks and correction clocks, can restrict an increase of a circuit scale and reduce a consumption current. SOLUTION: In a 2-bank 64-Mbit synchronous DRAM of an SMD clock control circuit scheme, a control logic & timing generator 15 comprises an input buffer circuit 17, a switch circuit 18 and a clock generator 19, and an SMD clock generation circuit 16 comprises a pulse generator 20, a delay circuit 21, an SMD array circuit 22, an SMD control circuit 23 and a locking range excess detector 24. An external clock CLK is used in a normal operation. For only a period from a read command to the completion of a burst operation, an SMD clock SCLK is used. When an SMD locking range is exceeded, the clock is automatically switched to the external clock CLK.
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