发明名称 |
CIRCUIT FOR CAPTURING FRAME SYNC SIGNAL IN RECEIVER |
摘要 |
A demodulator (1) produces I and Q symbol streams from a received PSK signal which is a time-multiplexed signal composed of a 20-symbol-long BPSK frame sync signal, a 20-symbol-long BPSK superframe identification signal, and an 8PSK digital signal. BPSK demappers (3) produce bit streams B0-B3 demapped according to a base criterion, which allows signal points to be the same along the Q-axis in the I-Q phase plane, and to criterions obtained by shifting the base criterion counterclockwise by pi /4, 2 pi /4 and 3 pi /4. First comparators (60-63) capture, from the bit streams B0-B3, patterns being different few bits at most than the frame sync signal. A predetermined time later, second comparators (64-67) capture patterns being different few bits at most than the superframe identification signal. A frame sync capture signal (SYN) is then produced by a generator (90). |
申请公布号 |
WO9934568(A1) |
申请公布日期 |
1999.07.08 |
申请号 |
WO1998JP05615 |
申请日期 |
1998.12.11 |
申请人 |
KABUSHIKI KAISHA KENWOOD;SHIRAISHI, KENICHI;HORII, AKIHIRO |
发明人 |
SHIRAISHI, KENICHI;HORII, AKIHIRO |
分类号 |
H04J3/06;H04L7/04;H04L27/22;(IPC1-7):H04L27/22 |
主分类号 |
H04J3/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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