发明名称 |
Fully digital clock synthesizer |
摘要 |
A fully digital clock multiplier capable of generating any N/M multiple of an input clock frequency with a precise duty cycle is provided. The input clock signal is divided by M to create a divided clock signal. The propagation of the input clock signal along a delay cell string during a half cycle of the divided clock signal is then measured. The measured propagation is then scaled by a factor N to select an appropriate delay cell string length within a ring oscillator for generating an output signal.
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申请公布号 |
US5920211(A) |
申请公布日期 |
1999.07.06 |
申请号 |
US19970825082 |
申请日期 |
1997.03.27 |
申请人 |
LSI LOGIC CORPORATION |
发明人 |
ANDERSON, MICHAEL B.;TABOR, GREGORY A. |
分类号 |
G06F11/36;H03K5/00;(IPC1-7):H03B19/00;H03K3/017 |
主分类号 |
G06F11/36 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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