Apparatus and method to determine a most significant bit

摘要

An adder using a leading zero/one detector (LZD) circuit and method of use determine an exact normalization shift with fewer logic levels and number of gates, resulting in saving considerable execution time to improve not only the timing as well as to reduce the size of the logic implementing the adder. In addition, a parallel method to locate the most significant digit is disclosed. Such an LZD circuit and method may be incorporated in an integrated circuit, and the LZD circuit includes a propagation value generator for generating a propagation value from input signals representing operands; and a location value generator for generating the location value from the generated propagation value.