| 摘要 |
An adder circuit includes a 4-2 compression circuit in which a NAND signal of a first input signal and a second input signal and an exclusive-OR signal of the first and second signals are produced. When the exclusive-OR output is true, a third signal is output as an intermediate carry-out signal while when the exclusive-OR signal is false, a NOT signal of the NAND signal is output as the intermediate carry-out signal. Therefore, the circuit can be reduced in size by reducing the number of necessary elements without sacrificing its high speed capability.
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