摘要 |
A column address selection circuit 1 is provided, which renders all column address signals (CSi), from a start address to a stop address designated by a column address signal (ADCd+ADCu), to be a selective level when a segment address selection signal (SASj) and a block write signal (BW) are at an active level. A segment address selection circuit 2 is provided, which renders all segment address selection signals (SASj), from the start address to the stop address designated by the column address signal (ADCu) of a superordinate side, to be a selection level to supply it to the column address selection circuit 1, when the block write signal (BW) is at the active level.
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