发明名称 |
Method and circuit for eliminating hold time violations in synchronous circuits |
摘要 |
Circuits and methods for eliminating hold time violations are disclosed. A DE-type flip-flop latches a data input signal on a data input terminal a fraction of a clock period before a triggering edge of the clock signal. The DE-type flip-flop provides a data output signal for a full clock period beginning after the triggering edge of the clock signal. The DE-type flip-flop includes a latch having its data output terminal coupled to the data input terminal of a flip-flop. The flip-flop clock input pin and the latch enable terminal of the latch are connected to a clock line. The DE-type flip-flop used in place of a standard flip-flop, in which a hold time violation occurs, eliminates the hold time violation.
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申请公布号 |
USH1796(H) |
申请公布日期 |
1999.07.06 |
申请号 |
US19960646643 |
申请日期 |
1996.05.02 |
申请人 |
SUN MICROSYSTEMS, INC. |
发明人 |
SRIVATSA, CHAKRA R.;MELANSON, RONALD J.;GREENHILL, DAVID J. |
分类号 |
H03K3/037;(IPC1-7):H03K3/037 |
主分类号 |
H03K3/037 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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