CLOCK DELAY CIRCUIT, OSCILLATION CIRCUIT USING THE SAME, PHASE LOCKED LOOP AND CLOCK GENERATION CIRCUIT

摘要

PROBLEM TO BE SOLVED: To finely adjust the oscillation frequency of a feed back loop without demaging the stability of an oscillation frequency by setting a mutual delay time so that a delay time difference between two continuous delay clock signals becomes shorter than a minimum delay time that can be realized in a delay element. SOLUTION: In the third period of an outer clock signal, a time difference between a two frequency division outer clock signal and the last fall edge of a multiple clock signal of a previous period is compared. When a phase difference exists between them, a first phase comparison circuit 19 outputs a first phase difference signal corresponding to the phase difference. The delay amount setting counter of a first delay amount switching circuit 20 is counted up accordingly. Thus, a delay time by a first DDL 16 and a delay time by a first clock delay circuit 17 become long. Then, the delay time is stabilized in a state where the time difference between the two frequency division outer clock signal and the last fall edge of the multiple clock signal in the previous period becomes not more than the delay time difference for one fine delay element.