发明名称 PLL CIRCUIT
摘要 PROBLEM TO BE SOLVED: To obtain a stable operation without the occurrence of unlocking, regardless of the nonuniformity in a producing condition by responding to the supply of a process fluctuation signal and executing an offset to permit the center value of a control voltage signal so as to be in the neighborhood of a level at the time of locking a frequency. SOLUTION: ADC 7 generates an offset voltage signal VF which is a fixed value for the offset for compensating the VC-fO characteristic of VCO4A, in corresponding to the saturation value of the control voltage signal VC. The bias generator of VCO4A converts the control voltage signal VC into a corresponding control current signal IB. A current control circuit converts the offset voltage signal VF into a corresponding current signal IF. An adder adds signals, outputs the control current signal and supplies it to a current control oscillator. The current control oscillator is controlled in a frequency corresponding to an input current signal so as to change the frequency fO of an oscillating signal FO, a bias generator aptitude gain is set and the operation is stabilized.
申请公布号 JPH11177416(A) 申请公布日期 1999.07.02
申请号 JP19970336927 申请日期 1997.12.08
申请人 NEC CORP 发明人 HASEGAWA MASARU
分类号 H03L7/093;H03L7/099 主分类号 H03L7/093
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