| 摘要 |
PROBLEM TO BE SOLVED: To provide a layout for a peripheral circuit region for reducing the size of a memory chip and line loading by arranging a fuse box between a row decoder and a sub array block control circuit. SOLUTION: A row redundancy circuit 3a is arranged between a row decoder 5a and a sub array block control circuit 6a, and a row redundancy circuit 3b is arranged between a row decoder 5b and a sub array block control circuit 6b. Similarly, row redundancy circuits 3c and 3d are arranged between the corresponding row decoder and sub array block control circuit. In this manner, by arranging the row redundancy circuit, a chip size can be minimized, line loading can be reduced, and power consumption can be reduced. |
