发明名称 FERROMAGNETIC MEMORY
摘要 PROBLEM TO BE SOLVED: To suppress reduction in a signal voltage margin and to improve reliability for a storage element of a ferromagnetic body memory, by making thin either a bit line width or a plate line width or both of them at a part where a bit line crosses a plate line, and reducing an area where the bit line overlaps with the plate line. SOLUTION: A line width of a bit line and a plate line is made thin at a region where a bit line crosses a plate line. More specifically, a 4 &mu;m plate line width is set to 1 &mu;m width and a 2 &mu;m bit line width is set to 1 &mu;m only at a part where the bit line crosses the plate line, thus setting the area of the overlapped part to 1 &mu;m<2> , hence reducing the coupling capacitance between the bit line and the plate line, at the same time effectively suppressing reduction in a signal voltage margin being obtained from a memory cell due to the coupling capacitance, reducing malfunction when reading data from the memory, and improving reliability of a storage element.
申请公布号 JPH11177035(A) 申请公布日期 1999.07.02
申请号 JP19970343263 申请日期 1997.12.12
申请人 NEC CORP 发明人 SHINOHARA SOTA
分类号 G11C14/00;G11C11/22;H01L21/8242;H01L21/8246;H01L21/8247;H01L27/10;H01L27/105;H01L27/108;H01L29/788;H01L29/792 主分类号 G11C14/00
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