SEMICONDUCTOR SUBSTRATE WITH EMBEDDED ISOLATING LAYER FOR INTEGRATED CIRCUITS

摘要

The invention relates to an integrated circuit with reduced parasitic capacitive influences and a method for producing same. The aim of the invention is to provide an integrated circuit with reduced parasitic capacitive influences and a method for producing same, in which the parasitic capacitive influences on individual elements of the integrated circuit are reduced. A further aim of the invention is for the technological process for producing the contact and printed circuit system of modern CMOS technology not to be adversely influenced during production and, in particular, to ensure that no additional planarising steps are required. To this end the invention provides for a partial isolating layer which is at least 5 mu m thick, is locally restricted to the area of the elements of the integrated circuit and is embedded in the semiconductor substrate. Those losses caused by parasitic influences which are affected by the specific electric resistance of the silicon substrate used are reduced markedly so that, for example, the quality of an integrated inductor can be raised by approximately 40 %, depending on the chosen thickness of the embedded isolating layer, and in relation to planar inductors based on conventional CMOS.