| 摘要 |
A lock detector for a phase locked loop circuit generates a lock detection signal indicative of whether the output signal is within a prescribed lock condition of the reference signal. The lock detector samples the control signal, examines a plurality of samples according to criteria associated with the prescribed lock condition between the reference signal and the oscillator output signal, and generates a lock signal indicative of the lock condition being met if the samples satisfy the criteria. In a favorable embodiment, the lock detector forms a first group of samples sampled at a rate controlled by the reference signal and a second group of samples at a rate controlled by the oscillator output signal of the phase locked loop. The samples are stored and shifted at the respective clock rates in respective shift registers. The contents of each stage of the shift registers are then examined according to a logic function. In an embodiment, the control signal includes first and second commands and is subjected to an initial logic function whose output is sampled by the shift registers.
|
