| 摘要 |
PROBLEM TO BE SOLVED: To synchronize an input data signal with an external clock signal in terms of bits. SOLUTION: An input data signal D1 is branched into plural delay signals which differ in a delay time, each delay signal is latched by an external input clock CK1, the latched signals are compared in terms of the phase, and a logic circuit 5 applies logical operation to the phase comparison result, and a latch circuit 6 with a protection function generates a delay time setting signal in the case of releasing hold based on the operation result. The delay time setting signal is held and sets a delay time of a variable delay circuit 1. The input data signal D1 is delayed by the variable delay circuit 1 and a data latch circuit 7 conducts but synchronization based on a clock CK 3. |
