Checking for combinational equivalence in circuits
摘要
A binary system has a facility to check for equivalence between a pair of combinational circuits. The process is based upon the use of binary decision diagrams (BDD) with integrated satisfiability (SAT) checking. The switching system is divided (20) into input (30) and an output section (40). Independent claims are provided for a computer system and computer program product.
申请公布号
DE19860061(A1)
申请公布日期
1999.07.01
申请号
DE19981060061
申请日期
1998.12.23
申请人
NEC CORP., TOKIO/TOKYO, JP
发明人
GUPTA, AARTI, PRINCETON, N.J., US;ASHAR, PRANAV, PRINCETON, N.J., US