SEMICONDUCTOR MEMORY, METHOD FOR PRODUCING SAID SEMICONDUCTOR MEMORY, AND IMPLANTATION MASK

摘要

The invention relates to a semiconductor memory arrangement. The aim of the invention is to prevent implantation-related lattice distortions in the area of the memory electrode. To this end, the first doped area (6) of the designated selection transistor, which is connected to the electrode, is more weakly doped than the second doped area (7) of the selection transistor, which is connected to the bit line. According to the invention, an implantation is carried out with an additional mask (Z), said mask covering the areas of the cell which are sensitive to damage and leaving free the second doped area and optionally, the transistors of the corresponding conduction type in the periphery.