| 摘要 |
The device is connected to a memory (7) by an address bus and a data bus. It is characterized in that, on a clock output, it delivers a clock signal (clki_b) to be sent to the clock input of the memory (6), in that the clock signal (clki) utilized for buffering the addresses and the data to be sent to the memory is the same, with the possible exception of having undergone signal inversion, as the one (clki_b) delivered on the clock output, and in that the same signal (clki_b) is utilized by the buffer (r1) receiving the data from the memory to buffer the data sent by the dynamic memory on the data bus. The applications relate to circuits for managing synchronous random-access memories. <IMAGE> |
