Gate electrode fabrication method

摘要

Methods for forming an integrated circuit, in particular for improving chemical vapor deposition of silicide on gate level interconnects in integrated circuits in order to reduce abnormal oxidation and nucleation of the silicide are disclosed. According to one aspect of the present invention, a method for forming a gate level interconnect in an integrated circuit includes forming a substrate, depositing a layer of gate oxide over the substrate, and depositing a layer of polycrystalline silicon over the gate oxide. A first layer of silicide is formed over the layer of polycrystalline silicon using a first chemical vapor deposition process at a first deposition temperature, and a second layer of silicide is formed over the first layer of silicide using a second chemical vapor deposition process at a second deposition temperature. In one embodiment, the second layer of silicide is formed directly over the first layer of silicide.