发明名称 Method of and apparatus for placing and routing elements of semiconductor integrated circuit having reduced delay time
摘要 A method of placing and routing elements of a semiconductor integrated circuit picks out a signal net, a driver of the signal net, and load cells driven by the driver among the elements of the integrated circuit, places the driver at a first position, defines a first range based on the first position, determines a second position in the first range, defines a second range based on the second position, and collectively places the load cells of a predetermined number in the second range. Namely, the method deals with a signal net in the integrated circuit, a driver of the net, and load cells driven by the driver. The method sets conditions on the signal net, driver, and load cells, when placing and routing the elements of the integrated circuit, to thereby reduce skew (skew time), wiring overhead, and time delay in the integrated circuit and speedily and easily place and route the elements.
申请公布号 US5917729(A) 申请公布日期 1999.06.29
申请号 US19970964318 申请日期 1997.11.04
申请人 FUJITSU LIMITED 发明人 NAGANUMA, MASAYUKI;TANIZAWA, TETSU
分类号 H01L21/822;G06F17/50;H01L21/82;H01L27/04;H01L27/118;(IPC1-7):G06F17/50 主分类号 H01L21/822
代理机构 代理人
主权项
地址