Power-on-reset circuit having reduced size charging capacitor

摘要

A power-on-reset (POR) circuit having a reduced sized charging capacitor is described which includes a voltage detection portion, a delay portion, and a POR signal generation portion. The voltage level detection portion functions to provide a level indicator signal after the power supply has reached a predetermined voltage level. The delay portion in response to the level indicator signal indicating that the power supply is greater than or equal to the predetermined voltage level charges a chargeable node to an inverter trip point voltage level in a predetermined delay time interval dependent on a capacitive element and a diode connected MOS device both connected to the chargeable node. The POR signal generation portion, in response to the voltage trip point level on the chargeable node, outputs a POR signal an extended time interval afterwards. The diode connected MOS device coupled to the chargeable node adds capacitance to the node and diminishes charging current as the node charges thereby allowing for the reduction in size of the capacitive element and a substantial reduction in size of the overall POR circuit layout size.