ASIC having flexible host CPU interface for ASIC adaptable for multiple processor family members

摘要

A CPU interface having an 8-bit mode in which the interface is capable of interfacing with a host CPU having 8-bit data bus, and a 16-bit mode in which the interface is capable of interfacing with a host CPU having a 16-bit data bus. The host CPU interface is further capable of switching between its 8-bit and 16-bit modes in real time in response to a 16-bit host CPU entering sections of 8-bit or 16-bit software. The interface also has "direct" and "indirect" addressing modes, so that the interface can send or receive time-multiplexed data, and receive address information on a single bus ("indirect" mode) or send or receive data, and receive address information in parallel on separate buses ("direct" mode).