Multiple bank memory

摘要

Programmable conductors (PC0-PC15) having equal width are arranged parallelly between y-select conductors such that specific section of the conductors (PC0-PC15) are arranged over the bank array (B0) and other section extends towards peripheral area. The conductors (PC0-PC15) are selectively connected to column factor conductor or power conductor through specific paths. Several y-select (C0-C15) conductors are connected parallelly to bit lines of bank array (B0,B1) and are selectively operated based on column address input to the decoder circuits (CDEC0-CDECO7). Several column factor conductors are arranged in parallel to word lines of bank arrays. The power conductor is arranged between the bank arrays in parallel to the word lines. An independent claim is included for bank array configuration method.