| 摘要 |
A semiconductor memory device is disclosed which comprises a regular row/column memory cell array having blocks obtained by dividing the memory cell array in the column and row directions, the blocks each being further divided in the column direction to form a plurality of sections, a first peripheral circuit [irregularly] provided between the blocks divided in the column direction, a second peripheral circuit provided between the blocks divided in the row direction and including a first decoder, a third peripheral circuit provided between the first peripheral circuit and the respective block and including a second decoder, and [a fourth peripheral circuit provided at the marginal portion of the memory cell array and including bonding pads and input protection circuit] sense amplifiers provided between neighboring sections in each of the blocks.
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