METHOD AND APPARATUS OF AN ADDRESS ANALYSIS FUNCTION IN A NETWORK EMPLOYING BOOLEAN LOGIC AND PROGRAMMABLE STRUCTURES FOR COMPLETE DESTINATION ADDRESS ANALYSIS

摘要

This invention relates to a method for and implementations of processing functions and programmable logic used for analyzing bit fields preferably related to analyzing network addresses in a communication network. The present invention uses processing functions based on calculation rules to analyze bit fields, where said calculation rules e.g. Boolean functions are implemented in hardware to analyze bit fields such as network addresses in one clock-cycle. The present invention further describes methods and implementations for using a prioritizing element in programmable logic devices to extend said bit field analysis to include prioritization, so that principles like longest prefix match can be used in network address analysis. Implementations with memory logic cells used in structures is presented.