发明名称 A SYSTEM AND METHOD FOR TRAP ADDRESS MAPPING FOR FAULT ISOLATION
摘要 The invention relates to the alteration of a segment (230) and an offset (240) used to form an effective address (220) of the default interrupt handler routine. The method comprising a number of steps. First, a trap address (210) of a default interrupt handler routine is provided. This trap address includes a segment (230) and an offset (240) normally used to calculate the effective address (220) via conventional circuitry. However, a unique segment is produced by performing an arithmetic operation on the segment (230). Thereafter, another arithmetic operation is performed to produce a unique offset. These unique segment and offset values may still be used by the conventional circuitry to still produce the same effective addresses so that only one default interrupt handler routine is required. While this alteration produces a unique segment (230) and offset (240) which can be assigned to an interrupt, the segment and offset are modified appropriately to still use a common default interrupt handler.
申请公布号 WO9931591(A1) 申请公布日期 1999.06.24
申请号 WO1998US24419 申请日期 1998.11.16
申请人 INTEL CORPORATION;ZIMMER, VINCENT, J. 发明人 ZIMMER, VINCENT, J.
分类号 G06F9/32;G06F12/02;(IPC1-7):G06F12/00;G06F11/00 主分类号 G06F9/32
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